1. Technical Field
The present disclosure relates to embedded systems.
2. Description of Related Art
The processing ability of an Advanced Reduced Instruction Set Computer Machine (ARM) processor in an embedded system is usually high. A number of peripheral processors may be arranged around the ARM processor when the processing ability of the ARM processor can not satisfy actual needs.
Referring to FIG. 1, a traditional embedded system 1000 includes a 64-bit ARM processor 1101 with 64 pins from P0-P63, eight 8-bit peripheral processors 1201˜1208, and eight 8-bit data flip-latches 1301˜1308. The 64 pins are divided into eight teams P0˜P7, P8˜P15, P16˜P23, P24˜P31, P32˜P39, P40˜P47, P48˜P55, and P56˜P63, each of which corresponds to a peripheral processor 1201 through 1208 respectively. Each flip-latch is connected among one team of the ARM processor 1101 and a corresponding peripheral processor, to transfer data between the team and the corresponding peripheral processor. For example, the first flip-latch 1301 is connected among the team P0˜P7 and the first peripheral processor 1201, and the eighth flip-latch 1308 is connected among the team P56˜P63 and the eighth peripheral processor 1208. With such configuration, when one peripheral processor needs to transfer 8-bit data to the ARM processor 1101 through a corresponding data flip-latch, the ARM processor 1101 is interrupted once to read the 8-bit data, and when two or more peripheral processors need to transfer data to the ARM processor 1101 simultaneously, the ARM processor 1101 is interrupted twice or more to read data from the two or more peripheral processors respectively, which may cause the ARM processor 1101 be interrupted frequently, thus, the processing efficiency of the ARM processor 1101 correspondingly decreases.